FPGA/ASIC Design Engineer (Silicon Engineering)

📋 Description

• Design ASICs/FPGA for Starlink; implement SoC blocks with Verilog/SystemVerilog
• Optimize designs for power, performance and area
• Lead full ASIC/FPGA design lifecycle from concept to lab validation
• Build tools to analyze data from orbit and in the lab
• Design test systems for interoperability and onboard verification
• Collaborate with software engineers to develop production software for your designs

🎯 Requirements

• Bachelor’s in Electrical/Computer Engineering, CS, or Physics
• 1+ years RTL design with SystemVerilog/Verilog/VHDL
• ASIC/FPGA integration experience; HDL toolchain (VCS/Questa/IES, Vivado/Quartus II)
• Python, C/C++, and Bash proficiency
• Experience with AXI/AHB/APB protocols and DSP/datapath blocks
• Strong lab debugging and cross-functional collaboration

🎁 Benefits

• Stock options and long-term incentives
• Employee Stock Purchase Plan
• Medical, vision, dental coverage
• 401(k) retirement plan
• Short/long-term disability and life insurance
• Paid parental leave, vacation and holidays