FPGA/ASIC Design Engineer (Silicon Engineering)

📋 Description

• Design ASICs/FPGA for Starlink; implement IP for complex SoCs using Verilog/SystemVerilog
• Participate in full design lifecycle from concept to backend; assist lab bring-up and validation
• Engage in high-level architectural design for FPGA/ASICs
• Collaborate with cross-functional engineers to advance Starlink terminals and satellites

🎯 Requirements

• Bachelor's degree in Electrical/Computer Engineering, CS, or Physics
• 1+ years RTL design experience with SystemVerilog, Verilog, or VHDL
• Master's in Electrical/Computer Engineering or related field preferred
• ASIC/FPGA system integration experience
• Python scripting proficiency
• AXI/AHB/APB protocols and HDL simulators experience