Contribute to validation of advanced chip designs.
Create and maintain UVM verification environments.
Write test plans, tests, and sequences for block- and chip-level verification.
Debug design issues based on architectural specifications.
Understand chip and subsystem architecture.
Collaborate with design and architecture teams to meet quality and schedule goals.

🎯 Requirements

BSEE/MSEE or equivalent in Electrical Engineering, Computer Science, or a related field.
Proficient in Verilog/SystemVerilog and UVM.
Comfortable working in Linux and with industry-standard EDA tools.
Solid grasp of verification methodologies and design processes.
Excellent teamwork and communication skills.
Experience with functional and code coverage analysis.

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