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python fpga asic systemverilog uvm📋 Description
- Define HW architecture and trade-offs for perf, area, power.
- Lead RTL development, integration, and verification throughout the design cycle.
- Partner with firmware and verification teams for silicon delivery.
- Mentor and review junior engineers’ work, promoting best practices.
- Provide design-in and bring-up support for customer projects.
🎯 Requirements
- Strong command of SystemVerilog for RTL design and digital architecture.
- Experience using simulation tools such as Questa, Incisive, or VCS.
- Skilled in scripting (Python, Perl, Tcl) for automation and workflow optimization.
- Proven experience in ASIC or FPGA design, synthesis, and timing closure.
- Strong analytical thinking and communication; manage complex priorities.
- 10+ years of relevant experience and a BSEE or MSEE degree.
🎁 Benefits
- Expertise in ASIC synthesis, timing constraints, CDC/RDC methodologies.
- Familiarity with UVM-based verification environments.
- Experience with high-speed memory technologies (HBM, GDDR, LPDDR, DDR).
- Understanding of AMBA AXI or CHI protocols.
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