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linux soc verification systemverilog uvm📋 Description
- Analyze architectural specifications and define verification requirements.
- Develop and maintain UVM-based verification environments.
- Create detailed test plans and develop corresponding test cases.
- Debug functional issues and contribute to root-cause analysis.
- Collaborate with design/architecture to align milestones and quality metrics.
🎯 Requirements
- Bachelor's or Master's in EE, CS, or related field.
- 7–10+ years in verification or similar roles.
- Strong SystemVerilog and UVM expertise.
- Familiar with Linux and standard EDA tools.
- Thorough understanding of pre-silicon design/verification flow.
- Excellent communication, documentation, and teamwork.
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