Responsible for digital ASIC verification at block and system level
Write and review test plans; develop test harnesses and sequences
Develop SystemVerilog testbenches (UVM and non-UVM)
Execute test plans; run regressions and coverage closure
Automate test cases using Python and MATLAB
Contribute towards pre-silicon verification, chip bring-up and post-silicon validation

🎯 Requirements

Bachelor's degree in EE, CS, or CE
1+ years of design verification and test bench development
Experience with verification methodologies such as UVM

🎁 Benefits

Stock options and long-term incentives
Medical, vision, and dental coverage
401(k) retirement plan
Disability and life insurance
Paid parental leave
Paid vacation and holidays

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