Design Verification Engineer (Silicon Engineering)

📋 Description

• Digital ASIC verification at block and system level
• Write/test plans; develop test harnesses and sequences
• Build SystemVerilog testbench infra (UVM and non-UVM) for DSP blocks
• Execute test plans; run regressions; close coverage
• Automate test cases with Python and MATLAB
• Contribute to pre-silicon verification, chip bring-up and post-silicon validation

🎯 Requirements

• Bachelor's degree in Electrical Engineering, CS, or CE
• 1+ years in design verification and testbench development
• Experience with UVM verification methodologies
• Python scripting for automation
• RTL design, chip bring-up, and post-silicon validation
• Ability to work extended hours and weekends as needed