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python matlab systemverilog uvm rtl📋 Description
- Responsible for digital ASIC verification at block and system level
- Write/review test plans; develop test harnesses and test sequences
- Develop SystemVerilog testbench infrastructure (UVM and non-UVM) for DSP blocks
- Execute test plans; run regressions; code and functional coverage closure
- Automate test case generation using Python and MATLAB
- Contribute toward pre-silicon verification, chip bring-up, and post-silicon validation
🎯 Requirements
- Bachelor's degree in electrical engineering, computer science or computer engineering
- 1+ years of experience with design verification and test bench development
- Experience with verification methodologies such as UVM
- Strong object-oriented programming knowledge
- Experience with scripting languages (Python) for automation
- RTL design, chip bring-up, post-silicon validation; extended hours as needed
🎁 Benefits
- Medical, vision, and dental coverage
- 401(k) retirement plan
- Short and long-term disability insurance
- Life insurance
- Paid parental leave
- 3 weeks vacation and 10+ holidays per year
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