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python matlab asic verification systemverilog📋 Description
- Digital ASIC verification at block and system level
- Write/review test plans; develop test harnesses and sequences
- Develop SystemVerilog testbench infra (UVM and non-UVM)
- Execute test plans; run regressions; close coverage
- Automate test cases with Python and MATLAB
- Contribute to pre-silicon, bring-up and post-silicon validation
🎯 Requirements
- Bachelor’s degree in electrical eng, CS or CE
- 1+ years in design verification and test bench development
- Advanced degree in electrical/computer engineering (preferred)
- UVM verification methodologies experience (preferred)
- Strong object-oriented programming knowledge
- Scripting languages: Python; MATLAB (preferred)
🎁 Benefits
- Medical, vision, and dental coverage
- 401(k) retirement plan
- Short/long-term disability insurance
- Life insurance
- Paid parental leave
- 3 weeks paid vacation; 10+ paid holidays
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