Collaborate with digital, photonics, and analog designers to create test plans.
Create UVM test benches for subsystem verification and support full-chip DV.
Develop Real Number Models (RNM) for photonics and AMS verification.
Contribute to the Golden Reference Model (GRM) and run emulations and formal DV.

🎯 Requirements

Master's degree (or higher) in Electrical or Computer Engineering
1-5 years of industry experience in Design Verification
SystemVerilog HDL proficiency
Knowledge of UVM or OVM verification methodologies
Experience with Xcelium, ModelSim, Questa, or VCS simulators
Perl or Python scripting experience

🎁 Benefits

Comprehensive Health Care Plan (Medical, Dental & Vision)
Retirement Savings Matching Program
Life Insurance (Basic, Voluntary & AD&D)
Generous Time Off (Vacation, Sick & Public Holidays)
Paid Family Leave
Flexible, hybrid workplace model

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