ASIC/SOC DFT Engineer (Silicon Engineering)

📋 Description

• Evaluate design readiness for scan insertion via RTL and Scan DRC
• Integrate and verify DFT fabrics/IP within subsystems
• Run and refine scan insertion using synthesis tools for max coverage
• Run ATPG analysis to ensure scan chain quality and basic coverage
• Run and debug non-timing and SDF-annotated gate-level simulations
• Create ATPG content for post-silicon testing and validate via gate-level sim

🎯 Requirements

• Bachelor's degree in electrical engineering, computer engineering or computer science
• 1+ years of professional experience working with ASICs
• Experience in scan insertion or DFT setup
• Understanding of ASIC design flow, methodologies, physical design, and verification
• Familiar with Verilog/SystemVerilog
• Familiar with UPF and DRC rule checking