Related skills
matlab systemverilog serdes ghz-speed rf analog front-end (afe) blocks for serdes📋 Description
- Design high-speed AMS circuits for transceivers interfacing with silicon photonics
- Investigate and evaluate new analog/mixed-signal topologies with chip architects
- Lead discussions with system, digital, analog, photonics to define block specs
- Document design simulations and verifications for design reviews
- Drive block-level floorplan, mask design views, and reviews
- Run post-layout and mixed-signal top-level simulations to validate integration
🎯 Requirements
- MS with 12+ years or PhD with 10+ years in GHz RF or broadband analog design
- Experience designing Analog Front-End blocks for SerDes
- Experience and deep understanding of Tx/Rx equalization techniques and circuits
- CMOS device characteristics, noise, linearity, high-speed circuit theory
- Experience collaborating with system/architecture teams to drive block/IP requirements
- Analog Mixed Signal circuit modeling and evaluation (SystemVerilog, Matlab, Python, VerilogAMS)
- Mentoring junior design engineers
🎁 Benefits
- Comprehensive Health Care Plan (Medical, Dental & Vision)
- Retirement Savings Matching Program
- Life Insurance (Basic, Voluntary & AD&D)
- Generous Time Off (Vacation, Sick & Public Holidays)
- Paid Family Leave
- Short Term & Long Term Disability
- Training & Development
- Commuter Benefits
- Flexible, hybrid workplace model
- Equity grants (applicable to full-time employees)
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